The TSMC CLN40G PLL is a general purpose deskew Phase Locked Loop (PLL) without external component.
The TSMC CLN40G PLL incorporates several frequency dividers to generate various output frequencies for different application. The output frequencies range from 350Mhz to 1460Mhz by divider setting and reference clock from 25Mhz to 180Mhz.
The feedback clock input pin can support the clock de-skew feature.
Bypass and power down mode are both available
- 25Mhz to 180Mhz input clock sup-port
- 1.8V analog supply and 0.9V digital supply
- Support clock deskew feature
- Input frequency bypass
- Power-down capability
- TSMC 40nm Logic 1.8V/0.8V with 1P7M, 5X1Z GDS