TSMC CLN5FF Digital Delay-Locked Loop

IGADLLY02A digital delay-locked loop is a high performance DLL for flash interface applications. IGADLLY02A is a high-speed Digital Delay-Locked Loop with master-slave digital control type for providing a fixed delay value which according to reference clock and delay setting. IGADLLY02A is designed for TSMC CLN5FF 1P6M and above 0.75 V/1.2 V process. Operating frequency is up to 3.6 GHz. The Digital Delay-Locked Loop is fabricated in CLN5FF TSMC standard cell could provide more reliable solution. The Digital Delay-Locked Loop IP is mainly for source synchronous system only. Any other application could not be guaranteed by this design and users should be aware of that.

• see the entire TSMC CLN5FF Digital Delay-Locked Loop datasheet
• get in contact with TSMC CLN5FF Digital Delay-Locked Loop Supplier