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TSMC CLN65LP 65nm DDR DLL - 164MHz-820MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock cycle. It uses a phase-locked analog delay line which rejects temperature and supply voltage variations, and has high supply noise rejection for very low jitter operation. TCI can configure this block to have almost any number of slaves (which delay the arbitrary signals) with a single master section (which establishes the time base) to minimize area and power. The slave delays can be independently set to precise values or dynamically adjusted after determining the boundaries of a data eye. The DDR DLL has excellent linearity and very high resolution. TCI can also configure this block to output multi-phase clocks directly from the reference clock.
Features
- Designed for high-speed DDR style interface applications.
- Generates precise delays that can be programmed from 0 to 360 degrees of the reference period.
- Delays multiple periodic or aperiodic signals independent of voltage and temperature.
- Delivers optimal jitter performance over a wide frequency range.
- Available in flexible form factors for easier integration.
Deliverables
- GDSII (100% DRC and LVS clean)
- LVS Spice netlist
- Verilog model
- Synopsys synthesis model
- LEF for clock generator PLL
- User Guidelines including:
- integration guidelines,
- layout guidelines,
- testability guidelines,
- packaging guidelines,
- board-level guidelines
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