Die-to-Die, 112G Ultra-Extra Short Reach PHY in TSMC (12nm, N7, N6, N5)
TSMC CLN6FF/7FF Die-to-Die Interface PHY
Process: TSMC 6 nm 0.75 V/1.8 V CMOS LOGIC FinFET Process or
TSMC 7 nm 0.75 V/1.8 V CMOS LOGIC FinFET Process
This test chip adopts TSMC 6 nm 0.75 V/1.8 V CMOS LOGIC FinFET Process
Layer & Device: High R Resistance, ULVT
Metal Scheme: 1P15M (1X_h_1Xa_v_1Ya_h_5Y_vhvhv_2Yy2Yx2R) or
1P13M (1X_h_1Xa_v_1Ya_h_5Y_vhvhv_2Yy2Z)
This test chip adopts 1P15M (1X_h_1Xa_v_1Ya_h_5Y_vhvhv_2Yy2Yx2R)
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