Low jitter, ultra-low power (<950uW) ring-oscillator-based PLL-2.4GHz
TSMC CLN7FFLVT 7nm DDR DLL - 360MHz-1800MHz
TCI can configure this block to have almost any number of slaves (which delay the arbitrary signals) with a single master section (which establishes the time base) to minimize area and power. The slave delays can be independently set to precise values or dynamically adjusted after determining the boundaries of a data eye. The DDR DLL has excellent linearity and very high resolution.
TCI can also configure this block to output multi-phase clocks directly from the reference clock.
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