English
You are here:
TSMC CLN80GT 80nm Multi Phase DLL - 500MHz-2500MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock. It delivers optimal jitter performance over a wide frequency range. The analog delay-line architecture used in our DLL design is internally isolated from supply noise for very low output jitter. The analog delay line also provides duty cyle correction.
Features
- Designed for high-speed interface applications.
- Generates precise multi-phase clocks directly from the reference clock.
- Delivers optimal jitter performance over a wide frequency range.
Deliverables
- GDSII (100% DRC and LVS clean)
- LVS Spice netlist
- Verilog model
- Synopsys synthesis model
- LEF for clock generator PLL
- User Guidelines including:
- integration guidelines,
- layout guidelines,
- testability guidelines,
- packaging guidelines,
- board-level guidelines
View TSMC CLN80GT 80nm Multi Phase DLL - 500MHz-2500MHz full description to...
- see the entire TSMC CLN80GT 80nm Multi Phase DLL - 500MHz-2500MHz datasheet
- get in contact with TSMC CLN80GT 80nm Multi Phase DLL - 500MHz-2500MHz Supplier
Multi Phase DLL
- TSMC CLN7FFLVT 7nm Multi Phase DLL - 1200MHz-6000MHz
- TSMC CLN7FF 7nm Multi Phase DLL - 800MHz-4000MHz
- TSMC CLN28HPC 28nm Multi Phase DLL - 700MHz-3500MHz
- TSMC CLN28HPC 28nm Multi Phase DLL - 350MHz-1750MHz
- TSMC CLN28HPC 28nm Multi Phase DLL - 175MHz-875MHz
- UMC L65LL 65nm Multi Phase DLL - 240MHz-1200MHz