Tuneable multi-port register file architecture

MiniMiser™ is a tuneable multi-port register file architecture that can support both low power and high-performance applications. Its unique implementation reduces power consumption by over 50% and gives developers a new way of optimising the power envelope for their design. By swapping off-the-shelf register files with MiniMiser significant power savings can be realised. By reviewing the application’s operational demands designers can further enhance this by introducing multiple performance modes tied to various operating voltages thereby ensuring the SoC is tuned to application need. As MiniMiser is not based on the foundry bit cell its single rail design means it can be directly connected to the system logic without the usual design headaches such as level shifters and static timing analysis challenges.

As wearable devices integrate increasing AI capabilities to enrich the user experience and provide product differentiation, ever more memory will be needed to support the computing demands driving up the overall power budget. Cutting and optimising power usage is critical to extending recharge windows and delivering a competitive product. As part of the system logic needed to deliver the computational capability register files are ubiquitous small blocks of memory providing either interim storage for calculations or interfacing between blocks in different clock domains. Typically, more efficient than flip-flop based register storage the standard bit cell based implementation is performance limited when developers look to move outside the typical operating norms. Multiple read/write ports, wide operating voltages and extremely high performance needs often drive designers back to power hungry flip-flops. MiniMiser elegantly addresses these challenges with dramatic power and area savings.

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