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Turbo Convolutional Code For 3GPP
The code rate of the TCC for 3GPP is 1/3. The data length is between 40 and 5114. The maximum data rate is 2 Mbps. Our implementation is fully compliant with the 3GPP specification. It takes 4 bit soft input for both the data and the parity symbols. The early termination mechanism can stop the decoding process once the optimal performance is achieved. An efficient interleaving process is employed to further improve the power efficiency. There is no need for external noise power estimation. The compact design makes it one of the smallest Turbo Convolutional Code on the market.
Features
- The following features are for 3GPP Encoder:
- Fully compliant with 3GPP (UMTS, WCDMA)specification. Support data block length 40 to 5114
- Available for Xilinx FPGA or ASIC implementation
- Encoder uses 561 CLB slices, 4 Block Rams and 3 multipliers in Virtex II. Or 568 CLB slices, 4 Block Rams and 3 multipliers in Spartan III, among the smallest on the market
- Clock speed reaches 125 MHz in Virtex II or 105 MHz in Spartan III
- Fully synchronous one clock design
- The following features are for 3GPP Decoder:
- Fully compliant with 3GPP (UMTS, WCDMA)specification. Support data block length 40 to 5114
- Available for Xilinx FPGA or ASIC implementation
- Decoder uses 1836 CLB slices, 18 Block Rams and 3 multipliers in Virtex II. Or 1865 CLB slices, 18 Block Rams and 3 multipliers in Spartan III, is the smallest on the market
- Clock speed reaches 75 MHz in Virtex II, supports 2 Mbps data rates at 8 iterations or 4 Mbps data rates at 4 iterations. Clock speed reaches 60 MHz in Spartan III, supports 2 Mbps data rates at 6 iterations or 4 Mbps data rate at 3 iterations
- No external noise power estimation
- 4 bit soft input for data and parity
- Early termination for power efficiency
- Power efficient interleaving operation
- Fully synchronous one clock design
Deliverables
- All the Turbo codes are available now. Deliverables include source code in VHDL or Verilog, netlist file for Xilinx FPGA, testbenches in VHDL or Verilog, and C/C++ source code for modeling and verification. Please contact us for more information
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