English
You are here:
Turbo Convolutional Code For 3GPP2
The Turbo convolutional code for 3GPP2 is fully compliant with the 3GPP2 specification. It supports all the code rates and all the data block lengths. The maximum data rate can be 2 Mbps at 8 iterations or 4 Mbps at 4 iterations. It takes 4 bit soft input for both the data and the parity symbols. The early termination mechanism can stop the decoding process once the optimal performance is achieved. There is no need for external noise power estimation. The compact design makes it one of the smallest Turbo Convolutional Code on the market.
Features
- The following features are for the 3GPP2 Encoder:
- Fully compliant with 3GPP2 (CDMA-2000) specification. Support all the data lengths and code rates
- Available for Xilinx FPGA or ASIC implementation
- Encoder uses 271 CLB slices, 12 Block Rams and 1 multiplier in Virtex II. Or 253 CLB slices, 12 Block Rams and 1 multiplier in Spartan III, among the smallest on the market
- Clock speed reaches 75 MHz in Virtex II or 65 MHz in Spartan III
- Fully synchronous one clock design
- The following features are for the 3GPP2 Decoder:
- Fully compliant with 3GPP2 (CDMA-2000) specification. Support all the data lengths and code rates
- Available for Xilinx FPGA or ASIC implementation
- Decoder uses 1608 CLB slices, 57 Block Rams and 1 multiplier in Virtex II. Or 1674 CLB slices, 57 Block Rams and 1 multiplier in Spartan III, among the smallest on the market
- Clock speed reaches 75 MHz in Virtex II, supports 2 Mbps data rates at 8 iterations or 4 Mbps data rates at 4 iterations. Clock speed reaches 60 MHz in Spartan III, supports 2Mbps data rates at 6 iterations or 4Mbps data rate at 3 iterations
- No external noise power estimation
- 4 bit soft input for data and parity
- Early termination for power efficiency
- Power efficient interleaving operation
- Fully synchronous one clock design
Deliverables
- All the Turbo codes are available now. Deliverables include source code in VHDL or Verilog, netlist file for Xilinx FPGA, testbenches in VHDL or Verilog, and C/C++ source code for modeling and verification. Please contact us for more information
View Turbo Convolutional Code For 3GPP2 full description to...
- see the entire Turbo Convolutional Code For 3GPP2 datasheet
- get in contact with Turbo Convolutional Code For 3GPP2 Supplier