SS M16550 OCP is a standard M16550 UART with standard OCP slave interface. It performs serial-to-parallel conversion on the data received from peripheral device and parallel-to-serial conversion on the transmitted data. programmable threshold on the receive FIFO allows the system designer to program the core for optimized throughput.
The OCP interface makes the core independent of the SoC bus and increases its reusability using the standard bus wrappers. Any processor / controller can configure the core and can read/write the data through the OCP interface at any time during the functional operation.
- Sixteen-byte deep transmit and receive FIFOs
- Line break generation, detection and reporting
- Prioritized interrupt control
- Modem handshake control and status reporting
- Programmable Receive FIFO threshold to improve throughput
- Programmability to enable/disable the transmit and receive FIFOs.
- Programmable baud generator divides any input clock by 2 to (216-1)and generates 16 x clock
- Special test mode feature to check baud rate generator counter logic
- Internal diagnostic capabilities with loop-back control, break, parity, overrun and framing error generation and detection
- SoC Integration
- Fully synthesizable Verilog RTL source code
- Documentation - Data Sheet, User Guide, Verification Description Document
- Self checking Verification Suite
- Synthesis and STA Scripts