UART Serial Interface Controller

Features

• UART-compatible interface
• AMBA APB3 bus
• Full duplex
• Custom baud rate generation
• 8x, 16x oversampling
• 5, 6, 7, 8, 9 bits data
• 1, 2 stop bits
• LSB or MSB mode
• Configurable parity
• Hardware flow control
• RS485 mode
• Maskable interrupts
• Dedicated upstream and downstream DMA interface
• Fully synthesizable synchronous design with positive edge clocking
• DFT ready

Benefits

• Synthesizable RTL Verilog source code
• Technology independent IP Core
• Suitable for FPGA and ASIC
• Silicon and FPGA proven
• Easy SoC integration
• Full implementation and maintenance support with individual approach
• Flexible licensing scheme

Deliverables

• Verilog RTL source code
• Verification suite
• Datasheet and integration guide
• C-header file
• Constraints
• Technical support

Block Diagram of the UART Serial Interface Controller IP Core

• see the entire UART Serial Interface Controller datasheet
• get in contact with UART Serial Interface Controller Supplier