UCIe 1.1 PHY (5nm)

The UCI Express Specification Revision 1.1 supports high-speed serialization and deserialization at 4GT/s, 8GT/s, 12GT/s, and 16GT/s with a 16-lane configuration, providing a 256-bit data bus width. It features automatic per-lane calibration, optional transmitter de-emphasis, and includes an Eye-Opening Monitor (EOM) and loopback test support for both internal and external testing.

• see the entire UCIe 1.1 PHY (5nm) datasheet
• get in contact with UCIe 1.1 PHY (5nm) Supplier