Chevin Technology’s 10G & 25G UDP/IP Offload Engine for FPGAs has low latency and bandwidth overhead, as it sends packets of data without confirming receipt. De-fragmentation is available as an option, so large UDP datagrams can be easily sent and received. The UDP IP core provides individual port numbers to differentiate between user requests, and receipt of data is verified using the checksum functionality.
Chevin Technology’s 10G &25G UDP/IP Offload Engine for Intel and Xilinx FPGAs is configurable, and simplifies integration by handling the complete Ethernet frame assembly. The UDP/IP Offload Engine is a mature IP core with proven success in customers’ projects. Reference designs are available for various boards to assist with integration and we offer our customers customised, expert engineering support packages to help meet project goals.