The logiISP Image Signal Processing Pipeline IP core is an Ultra High Definition (UHD) ISP pipeline designed for digital processing and image quality enhancements of an input video stream in Smarter Vision embedded designs based on Xilinx Zynq-7000 AP SoC, 7 Series and newer Xilinx All Programmable devices. The logiISP IP core accepts diversely formatted video inputs generated by different sensors and removes defective pixels, de-mosaics Bayer encoded video, makes image color and gamma corrections, filters the noise from the video, collects video analytics data for various control algorithms and manipulates video data formats and color domains. In addition to the standard IP core deliverables, Xylon offers licensable Auto White Balancing (AWB) and Auto Exposure (AE) processor-based control algorithms that work with the video analytics data collected by the ISP pipeline.
The logiISP IP core can be easily combined with the logiHDR High Dynamic Range (HDR) Pipeline IP core into advanced video processing pipeline capable to extract the maximum detail from high contrast scenes, i.e. scenes with objects highlighted by a direct sunlight and objects placed in extreme shades.
The logiISP Image Signal Processing Pipeline IP core is prepackaged for Xilinx Vivado IP Integrator (IPI) tool, requires no skills beyond general tools knowledge and can be used in same ways as Xilinx IP cores. Video system designers can easily setup the logiISP ISP pipeline configuration by selecting video input and output formats, switching on and off pipeline stages (blocks) and setting up all IP core’s parameters through an easy-to-use IPI GUI interface.