Ultra-low power 10 MHz dock multiplier from a low frequency reference
The Racyics® clock generator is designed to generate a 10 MHz dock from a low-frequency reference with as little power and area overhead as possible.
For highest flexibility, a wide range of reference frequencies is supported. The generated dock can be fed to the Racyics® ABB generator.
- The All Digital Frequency Locked Loop (ADFLL) architecture is reduced to the minimum amount of hardware necessary to generate a 10 MHz clock
- High energy efficiency: Only 5 pW are consumed during operation
- A reference clock divider allows reference clock frequencies from 32 kHz to 1 MHz
- Verilog simulation models
- .lib/.db timing and power models (NLDM)
- .lef layout abstract views
- Milkyway database
- GDSII files
- LVS netlist