ABB-enabled, All-Digital PLL clock generator for ultra-low power clocking in highly energy efficient Systems on Chip
The Racyics® Ultra-Low Voltage Clock Generator is targeted at Systems on Chip (SoCs) employing advanced power management techniques. The robust, fully digital architecture allows operation in a wide voltage and frequency range. Unique fast lock and instant frequency change features maximize the energy efficiency of the targeted systems.
- The fully digital architecture allows operation from 0.4 to 0.8V and from 20 Mhz up to 1 GHz.
- Very energy efficient, especially at low supply voltages: Only 100pW power consumption for a 100 MHz output clock at 0.5V
- A custom DCO allows fast lock-in and instant frequency changes during operation through direct tuning value calculation and without additional. hardware
- The Racyics® ABB enabled implementation reduces jitter at low supply voltages
- Verilog simulation models
- .lib/.db timing and power models (NLDM)
- .lef layout abstract views
- Milkyway database
- GDSII files
- LVS netlist