Ultimate Performance for Next-Generation Smartphones and Laptops
The Cortex-X4 core is implemented inside a DSU-120 DynamIQ™ cluster. It is connected to the DynamIQ Shared Unit-120 that behaves as a full interconnect with L3 cache and snoop control. This connection configuration is also used in systems with different types of cores where the Cortex-X4 core is the high-performance core.
The following figure shows an example configuration with four Cortex-X4 cores in a DynamIQ™ cluster.
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Arm Cortex-X4 IP
- 32-Bit RISC-V Embedded Processor and Subsystem. Maps ARM M-0 to M-4. Optimal PPA.
- LC3 / LC3plus Bluetooth LE Audio Codecs for Arm Cortex M55
- LC3 / LC3plus Bluetooth LE Audio Codecs for Arm Cortex M4 & M33
- ARM HSSTP PHY with Link Layer
- SPI Master / Slave Controller w/FIFO (APB Bus)
- eSPI & SPI Master/Slave Controller w/FIFO (APB, AHB, or AXI Bus)