This state of the art implementation of the AES-GCM algorithm provides privacy and authentication and can be configured for performance between 25 and 400Gbit/sec performance on modern FPGA devices. The main application is expected to be securing 100Gbit/sec OTN networks..
This is core builds on the technology in our DUPLEX-AES-GCM-10G product and extends it by supporting 1, 2, 4, 8 or 16 compute units in parallel. With a clock frequency of 195.5MHz each compute unit delivers 25Gbit/sec and at 391MHz each compute unit delivers 50Gbit/sec. The core is suitable for applications such as OTN where key changes are infrequent and the packets to be encrypted are all the same size. Significant area reductions are achieved by precalculating AES keyschedule information and information for use in the GF-Hash computation in software rather than calculating it on the fly with hardware.
This core is supplied as VHDL source code with a testbench which contains a behavioral model of AES-GCM and self-checks the hardware design against the model on a sequence of random packets.