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DDR3, DDR2, Multi-port Memory Controller IP Core
The DDR/DDR2/DDR3-SDRAM memory controller IP Core supports both Single Data Rate (SDR) and Double Data Rate (DDR / DDR2 / DDR3) SDRAM devices.
The memory controller IP Core is an assembly of modules (controller core, user ports and physical interface). According to the user needs, a top-level can be automatically generated with all modules included.
The controller core includes a multi-port arbiter and a command sequencer. It is optimized to achieve high bandwidth by mixing accesses to the different banks of the SDRAM. It generates burst of 8 data with auto-precharge option, allowing continuous data transfer in case of long bursts.
The user port includes FIFO (for both data and addresses). Each port can have a different data bus width (larger or smaller than the SDRAM bus width). The user port provides access to individual data. It manages the generation of SDRAM burst.
The user port can be configured with many different interfaces including AXI-4 and Avalon-MM.
The physical interface manages the double data rate and the source synchronous data sampling.
The memory controller IP Core is an assembly of modules (controller core, user ports and physical interface). According to the user needs, a top-level can be automatically generated with all modules included.
The controller core includes a multi-port arbiter and a command sequencer. It is optimized to achieve high bandwidth by mixing accesses to the different banks of the SDRAM. It generates burst of 8 data with auto-precharge option, allowing continuous data transfer in case of long bursts.
The user port includes FIFO (for both data and addresses). Each port can have a different data bus width (larger or smaller than the SDRAM bus width). The user port provides access to individual data. It manages the generation of SDRAM burst.
The user port can be configured with many different interfaces including AXI-4 and Avalon-MM.
The physical interface manages the double data rate and the source synchronous data sampling.
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Block Diagram of the DDR3, DDR2, Multi-port Memory Controller IP Core
