E801 is has the lowest cost and lowest power consumption among T-Head processors. It achieves the optimization of chip cost through a minimalistic instruction set and pipeline, and is applicable to traditional 8-bit MCU scenarios.
- Instruction set: T-Head ISA (32-bit/16-bit variable-length instruction set);
- Pipeline: 2-stage;
- General register: 16 32-bit GPRs ;
- Bus interface: Single bus;
- Tight coupling IP: Interrupt controller and timer;
- Multiplier: Slow multiplier;
- Interrupt response acceleration technology: Enhances the system's real-time performance to allow users to quickly enter the corresponding service program.
- Wireless connectivity;
- Smart Home Appliances.
Block Diagram of the Ultra-low-cost 32-bit processor IP Core