The 10G Ethernet MAC (XGMAC) for FPGAs is an ultra-low latency, low gate count 10Gbit IP that simplifies the FPGA integration of ultra-fast 10Gbit/s Ethernet.
XGMAC is an all- RTL design to achieve the lowest possible latency, and is fully compliant with the IEEE802.3 specification. The FIFO application interface can be configured for either Xilinx or Altera.
XGMAC is easily integrated into high end FPGAs such as Virtex 6, 7 series (Xilinx) & Stratix, Arria (Altera).
The smooth integration of the XGMAC into your product is supported by reference designs, concise code documentation, and access to expert engineers.
- Designed to IEEE 802.3-2008 Specification
- Low Latency 44.8 ns
- Integrated FCS CRC32 check/generate
- Small Footprint, 2749 LUTs
- Flow Control option with Pause packets
- Programmable max frame length
- Reconciliation Layer -Local /Remote Faults
- Programmable Inter Frame Gap
- Deficit Idle Count for maximum throughput
- Cut-through mode for lowest latency
- Store-and-forward for minimum app load
- MAC address filtering options
- Detailed traffic analysis statistics collection
- Optional MDIO master for controlling PHY
- Get up and running quickly with the reference design on an AlphaData ADMPCIE KU3, ADM-PCIE-8V3, ADM-PCIE-9V3 boards, or a Xilinx KC705 development board and a simple “ping” command line with the ICMP/ARP options. Use standard software TCP/UDP tools when integrated with the XGTCP IP block from Chevin Technology’s portfolio of IP blocks.
- Encrypted RTL/VHDL source code for simulation
- Encrypted compiled netlist
- Datasheet & User Guide to assist integration
- Reference Designs for Alpha-Data boards
- ADM-PCIE-KU3, ADM-PCIE-8V3, ADM-PCIE-9V3
- Simulation Test bench
- Build scripts for Vivado
- Support for integration into FPGAs
- Trade execution & monitoring
- Data Storage & Capture systems
- HPC / Big Data systems
- Signal processing systems
- Data Mining
Block Diagram of the Ultra low-latency 10Gbit/s Ethernet MAC