English
Switching regulator, inductor-based, PWM mode, high efficiency, DELTA standard
You are here:
Ultra Low Leakage Dual Port SRAM Compiler with Row/Column Redundancy Option - TSMC 40nm LP (CLN40lp)
Dolphin Technology maintains a broad IP portfolio of Memory Compilers, Specialty Memory and Memory Test & Repair (Memory BIST), providing SoC designers with solutions optimized for low power, high performance and high density across a broad range of process technologies. These solutions feature advanced power management capabilities - such as light sleep, deep sleep, power gating, dual rails and more - that meet even the most demanding low-power, low-leakage requirements.
View Ultra Low Leakage Dual Port SRAM Compiler with Row/Column Redundancy Option - TSMC 40nm LP (CLN40lp) full description to...
- see the entire Ultra Low Leakage Dual Port SRAM Compiler with Row/Column Redundancy Option - TSMC 40nm LP (CLN40lp) datasheet
- get in contact with Ultra Low Leakage Dual Port SRAM Compiler with Row/Column Redundancy Option - TSMC 40nm LP (CLN40lp) Supplier
memory compiler IP
- sROMet compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 1M
- sROMet compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 1M
- sROMet compiler - Memory optimized for high density and high speed - compiler range up to 2M
- Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Rail - compiler range up to 288 k
- Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Rail - compiler range up to 288 k
- Single Port, Ultra High Speed, GF 22FDX, SRAM Memory Compiler