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PHY IP for Bluetooth low energy, Thread, and Zigbee in TSMC (40nm, 55nm)
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Ultra-low-power 10-Bit, 100 KSPS, 1.8V CMOS A/D Converter
The KTAD100011 is a 10-bit monolithic sampling analog-to-digital converter (ADC) with a fully-differential wideband on-chip track-and-hold circuit that is capable of preserving high quality input signals beyond the Nyquist frequency. The ADC operates at various conversion rates up to 100KSPS, with outstanding dynamic performance over a wide bandwidth up to 500 KHz.
The ADC requires a single 1.8V power supply and consumes less than 162uW at 100KSPS with a 1.1MHz master clock.
The ADC is designed on a number of TSMC-compatible and other general 0.18um CMOS processes in leading foundries including SMIC, Jazz and HHNEC.
The IP is available in both soft core and firm core format.
The ADC requires a single 1.8V power supply and consumes less than 162uW at 100KSPS with a 1.1MHz master clock.
The ADC is designed on a number of TSMC-compatible and other general 0.18um CMOS processes in leading foundries including SMIC, Jazz and HHNEC.
The IP is available in both soft core and firm core format.
Features
- 1.8V single supply (1.6V to 2V operation)
- ENOB = 9.5 bit
- SFDR = 68dBc
- Linearity:
- DNL: ±0.5 LSB
- INL: ±1 LSB
- Ultra-low power ADC 162uW at 100KSPS with on-chip reference
- Differential input with > 500 KHz bandwidth
- On-chip track-and-hold
- Flexible analog input: 1Vp-p to 1.8Vp-p
- Flexible process options: multiple versions to fit both logic and analog processes
- Available in Jazz, SMIC, HHNEC and in TSMC compatible 0.18um CMOS
Benefits
- High-performance
- 9.4 ENOB with full-scale input @ 50 KHz with 1.1MHz master clock.
- Low power
- Consumes less than 162uW @ 100KSPS with on-chip reference.
- Flexible foundry/process options
- Designed in both TSMC compatible and non-compatible 0.18um CMOS processes with and without analog/RF options.
Deliverables
- High-level behavioral model (AHDL)
- Pin file (.LEF)
- GDSII
- Flat netlist
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