This IP core is available with a configurable number of ACS units to suit a range of throughput requirements. The default configuration instances 4 ACS units. The configurations with 1, 2, 4, 8 and 16 ACS units decode a message bit in 33, 17, 9, 5 and 3 clock cycles respectively. By implementing a register exchange traceback algorithm this core is suitable for applications with strict latency constraints. In particular the latency is equal to the traceback length. The regsiter exchange algorithm doesn’t require any RAM memory for storage.
The core can be used for streaming or packetised data applications. By using signed LLR input data it naturally supports de-puncturing by inserting zeros. The core provides automatic normalization of the path metrics, ensuring that overflow cannot occur.
- Constraint length 7.
- Generator polynomials g0 = 1338 g1 =1718.
- Register exchange traceback from best state.
- Optional trellis end state for packetised data.
- Optional trellis start state for packetised data.
- Low latency equal to block length.
- Signed 3-bit soft decision (LLR) inputs.
- De-puncturing support.
- Automatic normalization.
- Configurable number of ACS units.
- Parameterisable soft core
- Low Silicon area
- No memories
- Easy to optimise for the end application by configuring number of ACS units
- Low latency provided by register exchange traceback with fast flush
- Improved performance through best state determination
- Low gate count and area :
- Configuration: 3-bit soft decision, 35-bit traceback, 8 ACS units on TSMC CLN90LP 90nm LP
- Area = 0.081mm^2
- Gatecount = 37k
- Fmax = 120MHz