Ultra-Low Power Fractional PLL IP in in TSMC (12/16nm FFC, 22nm ULP/ULL, 28nm HPC+)

M31 ULFPLL is an ultra-low-power programmable fractional-N (ULF), phase-locked loop (PLL) for frequency synthesis. It can support a wide range of output frequencies with fine resolution, as well as supporting multiple input reference frequencies. With pure core power domain design implemented, M31 ULFPLL achieves an ultra-low-power solution. M31 ULFPLL is also ideal for use in noisy ASIC/SoC environments due to the excellent supply noise immunity. The lock-detect flag supports real-time monitoring of the phase-locked status. With an internal initial sequence applied to release from complex configurations and settings, M31 ULFPLL is available as a single macro and can be integrated into any ASIC/SoC easily.

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