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Ultra Low Power MP3 Decoder
iBexMP3x1 MP3 decoder ASIC/FPGA core is designed for low power MP3 applications. All decoding data paths are optimized to ensure the best performance with the least silicon area. The iBexMP3x1 is a consumer market proven silicon IP.
Features
- All MP3 decoding functions implemented at RTL level
- Smallest size (45 K gates plus 13 Kbytes data RAM)
- Lowest power consumption (clock required 9 MHz)
- Single clock synchronous design
- Support both ISO11172-3 and ISO13818-3 layer III audio decoding
- Straightforward interfaces for SoC applications
- Fully synthesizable technology independent of verilog RTL code
- Ten-bands equalizer with 64 steps for -20 to 20 dB gain
- Thirty-two steps volume control
Deliverables
- Synthesizable verilog source code
- Verilog testbench
Block Diagram of the Ultra Low Power MP3 Decoder IP Core
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MP3
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