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UltraLink D2D PHY
The Cadence® UltraLink™ D2D PHY IP is a high-performance, low-latency PHY for die-to-die connectivity targeted at the AI/ML, 5G, cloud computing, and networking markets. The UltraLink D2D PHY IP is an enabling technology for D2D and system-in-package (SiP) applications, which enable SoC providers to deliver more customized solutions that offer higher performance and yields while also shortening development cycles and reducing costs through greater IP reuse.
Features
- Silicon proven and prime for customer engagements today
- Supports multi-chip module (MCM) SoCs on organic substrates
- 40Gbps wire speed delivers up to 1Tbps/mm unidirectional bandwidth
- Achieves better than 10-15 BER without requiring FEC
- Flexible data rate from 20Gbps to 40Gbps
- Single-ended NRZ signaling scheme
- Built-in self-test features to ensure “known good die”
- Sideband for link management
- Interoperable between different technology nodes and foundry
Benefits
- 1Tbps/mm unidirectional bandwidth
- Low power and low latency
- Easy routing and straightforward integration
- Supports multi-chip module on organic substrates
- Better than 10-15 bit error rate (BER) without needing forward error correction (FEC)
Block Diagram of the UltraLink D2D PHY IP Core
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