As FFT lengths increase, FPGA and ASIC memory usage becomes more pervasive than logic usage. When the memory usage exceeds the on-chip memory capacity, it may require splitting the FFT algorithm processing and storing intermediate results in external memory. Here an "UltraLong FFT" is thus defined as an FFT length that exceeds the internal memory budget of the target device, necessitating data movement to external memory.
- The performance of a 2D FFT is limited by the bandwidth of the external memory. Each UltraLong FFT IP Core delivered by Dillon Engineering is configured to obtain maximum performance based upon the external memory architecture available. Fast synchronous SRAM is best, as the transpose is slowed by DRAM.