Xilinx offers an integrated 100 Gigabit per second (Gbps) Ethernet Media Access Controller (MAC) and Physical Coding Sublayer (PCS) core for high performance applications. The core is designed to the IEEE 802.3-2012 specification in the latest Virtex® UltraScale™ and Kintex® UltraScale FPGAs.
The Xilinx 100 Gbps Ethernet MAC and PCS core provides high-performance interconnect technologies for communications equipment and flexibility in implementing emerging interface standards. The PCS portion of the IP can be configured in CAUI-10 (10 lanes x 10.3125G), CAUI-4 (4 lanes x 25.78125G) or a dynamically switchable CAUI-10 and CAUI-4 mode.
- Supports 10 lanes x10.3125 CAUI-10, 4 lanes x25.78125G CAUI-4 or dynamically switchable CAUI-4 and CAUI-10 mode
- No charge license key enabled
- 1588 1-step and 2-step hardware time stamping
- Allows insertion of custom logic such as RS-FEC between the 100G Ethernet integrated block and GT
- Optional Frame Check Sequence (FCS) checking, adding and deleting
- Priority flow control
- Dynamic and static skew support
- PCS Lane Marker insertion and deletion