Xilinx offers an integrated 100 Gigabit per second (Gbps) Ethernet Media Access Controller (MAC), Physical Coding Sublayer (PCS), and IEEE 802.3bj Reed-Solomon Forward Error Correction (RS-FEC) Subsystem to enable new emerging optical solutions such as SR4, CWDM4, PSM4, or ER4f for high performance applications.
The Xilinx 100G Ethernet Subsystem provides high-performance interconnect technologies for communications equipment and flexibility in implementing emerging interface standards. The PCS portion of the IP can be configured in CAUI-10 (10 lanes x 10.3125G), CAUI-4 (4 lanes x 25.78125G) or a dynamically switchable CAUI-10 and CAUI-4 mode with optional built-in RS-FEC.
- Optional built-in 100G RS-FEC
- Supports 10 lanes x10.3125 CAUI-10, 4 lanes x25.78125G CAUI-4 or dynamically switchable CAUI-4 and CAUI-10 mode
- Requires license key available at no charge
- 1588 1-step and 2-step hardware time stamping
- Optional Frame Check Sequence (FCS) checking, adding and deleting
- Priority flow control
- Dynamic and static skew support
- PCS Lane Marker insertion and deletion
- OTN mapping mode