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UMC 0.11um AE/HS logic process Multi-Voltage BOAC SD3.0 I/O Cell library
UMC 0.11um AE/HS logic process Multi-Voltage BOAC SD3.0 I/O Cell library
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Logic Libraries IP
- High-Speed, High-Density and Low Power Memory Compilers and Logic Libraries for TSMC (65nm, 40nm, 28nm, 16nm)
- High-Speed, High-Density and Low Power Memory Compilers and Logic Libraries for GLOBALFOUNDRIES (55nm, 40nm)
- High-Speed, High-Density and Low Power Memory Compilers and Logic Libraries for HUALI (55nm, 40nm)
- High-Speed, High-Density and Low Power Memory Compilers and Logic Libraries for SMIC (65nm, 40nm)
- High-Speed, High-Density and Low Power Memory Compilers and Logic Libraries for UMC (40nm, 28nm)
- UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60) w/ Forward Bias. W/ deep Nwell.