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LTE NB-IOT (NB1) power optimized transceiver for cellular IoT
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UMC 28nm Logic and Mixed-Mode HPC Process, 1.8V Analog ESD IO cell Library
UMC 28nm Logic and Mixed-Mode HPC Process, 1.8V Analog ESD IO cell Library
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Logic Libraries IP
- High-Speed, High-Density and Low Power Memory Compilers and Logic Libraries for TSMC (65nm, 40nm, 28nm, 16nm)
- High-Speed, High-Density and Low Power Memory Compilers and Logic Libraries for GLOBALFOUNDRIES (55nm, 40nm)
- High-Speed, High-Density and Low Power Memory Compilers and Logic Libraries for HUALI (55nm, 40nm)
- High-Speed, High-Density and Low Power Memory Compilers and Logic Libraries for SMIC (65nm, 40nm)
- High-Speed, High-Density and Low Power Memory Compilers and Logic Libraries for UMC (40nm, 28nm)
- UMC 28nm HPC/LVT Logic and Mixed-Mode Process 12-track Standard Generic core cell library (C40)