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Low latency Network TAP IP-Core for full duplex 100M/1G Ethernet links
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UMC 40nm Low Power Process One Port Register File with 213 cell
UMC 40nm Low Power Process One Port Register File with 213 cell
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Memory Compiler
- sROMet compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 1M
- sROMet compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 1M
- sROMet compiler - Memory optimized for high density and high speed - compiler range up to 2M
- Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Rail - compiler range up to 288 k
- Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Rail - compiler range up to 288 k
- Single Port, Ultra High Speed, GF 22FDX, SRAM Memory Compiler