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MIPI D-PHY 1.5Gbps (4-lanes TX/RX, PLL Integrated) TSMC 28HPM
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UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy and LVT peripheral
UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy and LVT peripheral
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Memory Compiler
- sROMet compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 1M
- sROMet compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 1M
- sROMet compiler - Memory optimized for high density and high speed - compiler range up to 2M
- Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Rail - compiler range up to 288 k
- sROMet compiler - TSMC 40 nm uLPeFlash - Non volatile memory optimized for high density and low power - Dual Voltage - compiler range up to 1M
- Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Rail - compiler range up to 288 k