English
You are here:
UMC 40nm LP Logic Process one-port register file for area optimize with LVT peripheral
UMC 40nm LP Logic Process one-port register file for area optimize with LVT peripheral
View UMC 40nm LP Logic Process one-port register file for area optimize with LVT peripheral full description to...
- see the entire UMC 40nm LP Logic Process one-port register file for area optimize with LVT peripheral datasheet
- get in contact with UMC 40nm LP Logic Process one-port register file for area optimize with LVT peripheral Supplier
Memory Compiler IP
- Single Port, Low Voltage, GLOBALFOUNDRIES 55LPX with Flash, HVt & Svt, SRAM Memory Compiler
- Single Port, Low Voltage, GLOBALFOUNDRIES 28SLP, HVt & Svt, SRAM Memory Compiler
- Single Port, Ultra High Speed, GF 22FDX, SRAM Memory Compiler
- Single Port, Ultra Low Leakage, GF 22FDX, Single Port Compiler
- Single Port, Low Voltage, GLOBALFOUNDRIES 28SLP, HVt & Svt, ROM Memory Compiler
- Dual Port, Low Voltage, GF SLP, HVt & SVt, SRAM Memory Compiler