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UMC 40nm LP/RVT Logic Process 1.8V ONFI 3.2 BOAC I/O cell library
UMC 40nm LP/RVT Logic Process 1.8V ONFI 3.2 BOAC I/O cell library
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Logic Libraries IP
- High-Speed, High-Density and Low Power Memory Compilers and Logic Libraries for TSMC (65nm, 40nm, 28nm, 16nm)
- High-Speed, High-Density and Low Power Memory Compilers and Logic Libraries for GLOBALFOUNDRIES (55nm, 40nm)
- High-Speed, High-Density and Low Power Memory Compilers and Logic Libraries for HUALI (55nm, 40nm)
- High-Speed, High-Density and Low Power Memory Compilers and Logic Libraries for SMIC (65nm, 40nm)
- High-Speed, High-Density and Low Power Memory Compilers and Logic Libraries for UMC (40nm, 28nm)
- Foundation IP (Memory Compliers & Standard Cell Libraries)