UMC 55nm eFlash/HVT Logic Process 7-track PowerSlash Kit cell library
View UMC 55nm eFlash/HVT Logic Process 7-track PowerSlash Kit cell library full description to...
- see the entire UMC 55nm eFlash/HVT Logic Process 7-track PowerSlash Kit cell library datasheet
- get in contact with UMC 55nm eFlash/HVT Logic Process 7-track PowerSlash Kit cell library Supplier
Logic Libraries IP
- High-Speed, High-Density and Low Power Memory Compilers and Logic Libraries for TSMC (65nm, 40nm, 28nm, 16nm)
- High-Speed, High-Density and Low Power Memory Compilers and Logic Libraries for GLOBALFOUNDRIES (55nm, 40nm)
- High-Speed, High-Density and Low Power Memory Compilers and Logic Libraries for HUALI (55nm, 40nm)
- High-Speed, High-Density and Low Power Memory Compilers and Logic Libraries for SMIC (65nm, 40nm)
- High-Speed, High-Density and Low Power Memory Compilers and Logic Libraries for UMC (40nm, 28nm)
- UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60). W/O deep Nwell