The macro M16550, implements a synchronous universal asynchronous receiver/transmitter, which provides an interface between a microprocessor and a serial communication channel.
This macro can be customized according to specific needs (application-specific requirement). Any other pre-designed functions can be integrated into the FPGA. FPGA density and I/O requirements can be defined according to customer specification.
- Single-chip synchronous UART
- Functionally based on the National Semiconductor Corporation NS16550 device
- Designed to be included in high-speed and high-performance applications
- System clock up to 150 MHz
- CPU independent interface
- Complete asynchronous communication protocol including :
- 5,6,7 or 8-bit data transmission
- Even/Odd or no parity bit generation and detection
- Start and Stop bit generation and detection
- Line break generation and detection
- Receiver Overrun and framing detection
- Up to 1M baud (system frequency dependent)
- 1 to 65535 divisor generates 16X clock
- Buffered transmit and receive registers
- Transmitter and receiver are buffered with 16 Byte FIFO, plus 3 error bits per data byte on receiver
- Polled or interrupt mode
- Loopback mode
- VHDL Source code
- VHDL Test Bench for behavioural and gate level simulation.
- Data Sheet and Reference Guide
- User’s guide : Simulation, Synthesis and Place and Route procedures.
- Constraint File