The Ziptilion Bandwidth IP accelertes the main memory bandwidth with up to 50%. The IP core packages a novel and proprietary technology that accelerates the limited off-chip bandwidth of main memories through real-time, general-purpose and on-the-fly memory data compression. The product benefit is significantly more main memory bandwidth at unmatched power efficiency.
Ziptilion Bandwidth IP is integrated in the memory subsystem of the SoC, close to the memory controller so that it can intercept all the memory traffic to/from DRAM to compress and decompress the data on-the-fly. The effect of compression is transparent to the CPU/accelerator subsystem as well as to the operating system and applications. Similarly, the memory controller is also unaware that the transmitted/received memory data is compressed. In essence, data compression and decompression, compaction as well as addressing the compressed memory space are handled automatically, transparently and hardware-accelerated by the IP.