The DesignWare USB 1.1 Controllers support Full and Low Speed based on USB specification from the USB Implementer Forum. The DesignWare USB 1.1 IP offering consists of the USB 1.1 Device and USB 1.1 OHCI Host controllers for integration into SoCs, and Verilog testbench for integration testing. These elements enable quick development of SoC designs incorporating the USB 1.1. The DesignWare USB 1.1 IP is targeted for SoCs requiring the smallest area and lowest power, such as those used in IoT applications.
The DMA in the Device controller and list processor in the Host controller reduce interrupts to the CPU/MPU and bus, reducing power consumption and leaving MIPS and bus bandwidth for other functions.
The DesignWare USB Digital Controllers offer easy integration, reliable data transfer speeds, and low overall power consumption. As the leading supplier of USB IP for more than a decade, Synopsys provides designers with efficient USB IP for cost effective integration into system-on-chip designs. Synopsys’ expertise in developing and supporting USB IP enables us to build a low risk, high quality USB IP solution.
- Fully supports Full Speed and Low Speed (USB 1.1 Speeds) specifications
- Low gate counts, starting at 22k gates
- Low integration effort required for faster time-to-market
- Verilog testbench includes a USB test environment and integration tests that can be ported to the system level
- Compatible with open source and commercially available drivers to reduce software engineering effort Hibernation option for additional power savings
- Control and status registers for reconfiguring the controller through firmware for maximum flexibility Bus interface unit with ARM® AMBA® AHB™ includes a DMA controller – Reduces CPU interrupts – Enhances AHB throughput
- Hibernation add-on option adds wakeup and power control support for: – Reduced power consumption by stopping the PHY clock when USB is suspended or the session is not valid – Further power reduction with AHB clock-gating and partial power-down methods
- Low gate count to save area
- Low-power architecture
- Silicon proven, shipped in billions of units
- Supports USB 1.1 Full and Low Speeds
- Host and Device functions available
- AHB interface for rapid integration
- Save software engineering effort by using drivers for OHCI-compatible Host
- Synopsys coreConsultant tool
- Verilog RTL source code
- ASIC and FPGA synthesis example scripts
- Verilog testbench
- Touch screen