The USB 2.0 Device Controller IP Core is an USB 2.0 compliant device core with optional PCI, Custom, or AHB master/slave interfaces.
The USB 2.0 device core supports 480 Mbit/s in High Speed (HS) mode. 12 Mbit/s in Full Speed (FS) mode, and 1.5 Mbit/s in Low Speed (LS) mode. The Arasan USB 2.0 Device IP Core supports up to 30 configurable IN/OUT non-control endpoints. Each noncontrol endpoint has anendpoint controller that supports interrupt, bulk, and isochronous transfers. There is one control endpoint that handles the setup, data, and status stages during control transfers. Auto Validation, Manual Validation, or Fly mode can be selected to reduce loading of the hostCPU during in-transfer operations. The USB 2.0 Device IP Core includes a DMA controller for handling high-speed data transfers between the USB 2.0 device core and PCI/Custom/AHB interface.
With the addition of an ULPI Wrapper, the Arasan USB 2.0 Device IP Core can be connected directly to a standard UTMI or 8-bit ULPI transceiver.
The USB 2.0 Device IP Core is an RTL design in Verilog that implements an USB device controller on an ASIC or FPGA. The core includes RTL code, test scripts and a test environment for full simulation verifications. Licensees include Micro Linear, Focus Semiconductors, Beceem Communications and others.
High speed support: 480 Mbit/s
Full speed support: 12 Mbit/s
USB 2.0 Compliant
High/Full speed support using 8/16 bit UTMI/ULPI interface
Master DMA implementation for each endpoint
Optional PIO Mode for each endpoint (can be used for Interrupt endoints)