The FHG USB EHC is a scalable, high performance IP-Module for usage in ASIC- and FPGA-designs to integrate full-/low-speed USB 2.0 host functionality in an embedded system. It provides an ease of use programming interface for the usage of almost every 16/32 bit microcontroller or DSP.
The FHG USB EHC supports up to 32 hardware data pipes. Every of these data pipes can be configured with a fixed address/endpoint and transfer parameters. If more data pipes are required, these assignments may be reconfigured during operation. Therefore, the real number of available pipes can be much larger than the number of hardware pipes using a corresponding firmware library. All transfer modes are supported (control, interrupt, isochronous and bulk transfer).
- Fully compliant to USB Specification 2.0 and the On-The-Go Supplement, Revision 1.0
- Full-/Low-Speed host capability (12Mbps/1.5Mbps)
- Supports OTG Session Request Protocol (SRP)
- Scalable number of pipes (max. 32 pipes)
- Scalable number of downstream ports
- Supports all transfer types (Control, Interrupt, Bulk and Isochronous)
- Pipe direction, transfer type and fifo size can be configured during run-time
- Supports hardware based scheduling and enhanced large buffer management
- Automatic retry for corrupted data packets
- Configurable for 16 or 32 bit data interface (64 bit in preparation)
- AMBA AHB ready (AHB slave interface for configuration, AHB master DMA interface with Single-Port RAM for payload data)
- AMBA AHB interface testet with Synopsys Amba Verification Suite
- PCI ready
- Dual-Port RAM interface available with scalable memory size
- Suspend/Resume/Remote Wakeup support
- Technology independent RTL implementation
- PCI evaluation module available
- Generic USB Host Software Stack with several class drivers available
- Optional OHCI and UHCI software emulation
- With the features described above, the FHG USB EHC brings an USB interface to your system, which is highly efficient from software’s point of view:
- All USB related timing critical features are realized in hardware. Therefore, for normal operation software has only to manage the enumeration process
- Once a pipe or channel is established, the only task of the software is to provide data buffers (entire USB protocol is managed by hardware, including data toggle, retry, polling of periodic pipes).This reduces the number and frequency of software interrupts to an minimum.
- The required interrupt latency time does not depend on the timing required by the USB packet level, but on the size of data buffers and pipe bandwidth.
- Typical USB devices working with the Embedded USB Host Controller are for example hard disk devices,
- multimedia devices, imaging devices, high speed network or industrial applications.
- One of the following LICENSES:
- VHDL source code for ASIC designs
- Synopsys Design Ware Component for ASIC designs
- VHDL/Verilog Netlist for FPGA designs (Xilinx/Actel/Altera)
- (Other license models upon request)
- The DESIGN KIT contains the following parts:
- The IP component, depending on the selected license
- VHDL/Verilog pre-compiled simulation models
- VHDL/Verilog USB 2.0 compliance test suite
- IP integration guideline
- Synthesis scripts
- PCI evaluation board