The FHG USB2 DEV is a scalable, high performance IP-Module for usage in ASIC- and FPGA-designs to
integrate high-/full-speed USB 2.0 device functionality with SRP (Session Request Protocol) to an embedded system. It provides an ease of use programming interface for the usage of almost every 16/32 bit microcontroller or DSP. The core supports direct RAM access as well as several DMA modes for data exchange with the main memory.
The FHG USB2 DEV supports up to 16 pipes. Pipe 0 is reserved to work as bi-directional control pipe. Every other pipe can be configured with an endpoint number and transfer parameters.