English
You are here:
USB 2.0 nanoPHY in TSMC (65nm, 55nm, 40nm)
The Synopsys DesignWare® USB 2.0 nanoPHY provides designers with a complete Physical Layer (PHY) IP solution, designed for low power mobile and consumer applications such as next generation handheld game machines, feature rich smart phones, digital cameras and portable audio/video players. The DesignWare USB 2.0 nanoPHY IP delivers approximately half the power and area, compared to other solutions, for longer battery life and lower silicon cost. Designed for high yield, the DesignWare USB 2.0 nanoPHY implements architectural features that make it less sensitive to variations in foundry process, device models, package and board parasitics.
View USB 2.0 nanoPHY in TSMC (65nm, 55nm, 40nm) full description to...
- see the entire USB 2.0 nanoPHY in TSMC (65nm, 55nm, 40nm) datasheet
- get in contact with USB 2.0 nanoPHY in TSMC (65nm, 55nm, 40nm) Supplier
Video Demo of the USB 2.0 nanoPHY in TSMC (65nm, 55nm, 40nm)
USB 2.0 has been around for over 20 years and is the world's most popular wired interconnect standard. Join Morten Christiansen and Gervais Fong as they discuss how the new eUSB2 standard enables USB 2.0 connectivity for SoCs in the most advanced process nodes.