English
You are here:
USB 2.0 nanoPHY in TSMC (65nm, 55nm, 40nm)
The Synopsys DesignWare® USB 2.0 nanoPHY provides designers with a complete Physical Layer (PHY) IP solution, designed for low power mobile and consumer applications such as next generation handheld game machines, feature rich smart phones, digital cameras and portable audio/video players. The DesignWare USB 2.0 nanoPHY IP delivers approximately half the power and area, compared to other solutions, for longer battery life and lower silicon cost. Designed for high yield, the DesignWare USB 2.0 nanoPHY implements architectural features that make it less sensitive to variations in foundry process, device models, package and board parasitics.
Features
- Complete mixed-signal physical layer for single-chip USB 2.0 OTG and non-OTG applications
- Low power: <100mW (during HS packet transmission)*
- Small area: ~ 0.6mm2 *
- High yield—Architecture designed to improve key operating margins by having less sensitivity to variations due to foundry process, chip and board parasitics, and process device model variations
- Low pin count
- USB 2.0 Transceiver Macrocell Interface (UTMI+ Level 3) specification 8-bit interface at 60 MHz operation and 16-bit interface at 30 MHz operation
- Hi-Speed (480 Mbps), Full-Speed (12 Mbps), and Low-Speed (1.5 Mbps) operation is compliant to the USB OTG Supplement
- Supports all OTG features, including Host Negotiation Protocol (HNP) and Session Request Protocol (SRP)
- Designed for rapid integration with Synopsys’ USB device and host controllers
- On-chip PLL reduces clock noise and eliminates externalclock generator requirement
- Built-in Vbus pulsing and discharge SRP circuitry
- Built-in Vbus threshold comparators
- Support for off-chip charge pump regulator to generate 5V Vbus signals
- Designed for minimal power dissipation for low-power and buspowered devices
- Suspend, resume, and remote wakeup mode support
- USB 2.0 test mode support
- Built-in self test features to confirm Hi-Speed, Full-Speed,and Low-Speed operation
- Minimal external component cost; requires one external resistor and crystal (optional)
- Implements foundry Design for Manufacturing (DFM) Rules for 65nm and 40nm processes
- Based on Synopsys’ industry leading USB Implementers Forum certified Hi-Speed USB 2.0 PHY architecture
Benefits
- Designed for advanced manufacturing processes, the USB 2.0 nanoPHY is targeted to leading 65nm and 40nm low-power, low leakage, generic, and high performance CMOS digital logic processes
- Integrates high-speed mixed-signal, custom CMOS circuitry designed to the UTMI+ Level 3 specification Supports the USB 2.0 480 Mbps protocol and data rate (Hi-Speed)
- Backward compatible to the USB 1.1 legacy protocol at 1.5 Mbps (Low-Speed) and 12 Mbps (Full-Speed)
- Can be connected with a Hi-Speed and OTG subsystem to perform as a standard Hi-Speed, Dual-Role Device (DRD), operating as either a fully USB 2.0 Hi-Speed compliant peripheral or an OTG host
View USB 2.0 nanoPHY in TSMC (65nm, 55nm, 40nm) full description to...
- see the entire USB 2.0 nanoPHY in TSMC (65nm, 55nm, 40nm) datasheet
- get in contact with USB 2.0 nanoPHY in TSMC (65nm, 55nm, 40nm) Supplier