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USB 2.0 PHY in TSMC(6nm, 7nm, 12nm, 16nm, 22nm, 28nm, 40nm, 55nm, 65nm, 90nm)
M31 provides customers the next generation of USB 2.0 IP with an extremely compact die area and lower active and suspend power consumption. M31 utilizes a whole new design architecture to implement the USB 2.0 IP without sacrificing the performance associated with USB 2.0. The USB 2.0 IP is not only suitable for USB peripherals, but also an optimized solution for SOCs that desire multiple USB ports.
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