USB 2.0 PHY in TSMC(7nm, 12nm, 16nm, 22nm, 28nm, 40nm, 55nm, 65nm, 90nm)

M31 provides customers a next generation USB 2.0 IP which delivers an extremely smaller die area and lower active and suspend power consumption. M31 uses a whole new design architecture to implement the USB 2.0 IP without sacrificing USB 2.0 related performances. The USB 2.0 IP is not only suitable for USB peripherals but also an optimized solution for SOC which is
eager for multiple USB ports.

• see the entire USB 2.0 PHY in TSMC(7nm, 12nm, 16nm, 22nm, 28nm, 40nm, 55nm, 65nm, 90nm) datasheet
• get in contact with USB 2.0 PHY in TSMC(7nm, 12nm, 16nm, 22nm, 28nm, 40nm, 55nm, 65nm, 90nm) Supplier