USB 2.0 PHY IP Device/Host/OTG/Hub (Silicon proven in UMC 55SP /EF)

The USB2.0 PHY IP is a complete physical layer (PHY) IP solution designed for peak performance. The USB2.0 IP implements a High-Speed USB 2.0 transceiver for use with either host, device and Hub function controllers. Compliant with the UTMI+ level 3 specification, the USB2.0 PHY IP integrates mixed-signal circuits to support High-Speed data rate at 480Mbps and is backward compatible to Full-Speed (12Mbps) and Low-Speed (1.5Mbps) data rates. The USB2.0 PHY IP transceiver is optimized for low power consumption and minimal die area without sacrificing performance and high-data throughput. The USB2.0 PHY IP comprises a complete on-chip physical transceiver solution with Electrostatic Discharge (ESD) protection, clock generation block provided by an internal PLL, and a resistor termination calibration circuit to ensure full support for host and device functionality.

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