USB 2.0 PHY IP, Silicon Proven in SMIC 40LL

A complete physical layer (PHY) IP solution designed for outstanding performance and minimal power consumption is the USB2.0 PHY IP. The USB2.0 IP implements the High-Speed USB 2.0 transceiver, which can be used with hosts, devices, or OTG function controllers. The USB2.0 PHY IP, which supports both Full-Speed (12 Mbps) and Low-Speed (1.5 Mbps) data rates, comes after the UTMI+ level 3 specification. High-speed data transmission @ 480Mbps can be accomplished by combining several mixed-signal circuits. The enhanced USB Battery Charging standards, which are designed for mobile and consumer product applications, are also supported by the USB2.0 PHY IP. Small chip size and low power consumption of the USB2.0 PHY IP transceiver did not affect performance or data throughput. The USB2.0 PHY IP offers a full on-chip physical transceiver solution with Electrostatic Discharge (ESD) protection, a clock generating block provided by an internal PLL, and a resistor termination calibration circuit in order to fully enable host and device functionality.

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