The SL200 is a Mixed-signal Core that can be manufactured stand alone or integrated with the Serial Interface Engine (SIE) and any system functions. The design has been mapped into different process technologies. The design is certified for Compliance and is integrated in more than 10 millions chips in production
The SL200 complies with UTMI specifications and consists of the following blocks: The Analog Front End (AFE), the Bit Stuffer, the Bit un-stuffer, the NRZ encoder and the NRZ Decoder.
The SL200 is offered in the following forms:
* A stand alone chip.
* A core that can be integrated with the SIE and other application specific logic.
* Bundled with our SL250 SIE core.
- GDSII Layout data base.
- LEF of pin sizes and locations
- Encrypted Verilog code
- Synthesis Timing Model
- Documentation including Design Manual and Testability.
- If the SL200 is delivered in a core form, the deliverables consist of GDSII data base, encrypted Verilog for simulation, Timing model (.lib) and documentation