USB 3.0/2.0 PHY TSMC 28HPC

Features

• Integrated BIST pattern generator and checker with numerous programmable modes for stand-alone tests
• Programmable pre-emphasis and amplitude for the transmitter
• USB 2.0 PHY included for backward compatibility, as defined in USB specifications
• Low-power and ultra-low-power support through U0, U1, U2, and U3 power modes
• 8b/10b encoding/decoding implemented in hardware
• Support for full-swing and low-power swing transmitter

Benefits

• Ease-of-use - system integration kit reduces system integration and signal integrity issues
• Reduced test cost in mass production - BIST circuit
• Greater functional testing - datapath loopback

Deliverables

• Verilog models for PHY modules
• Verilog testbench with configuration files and sample tests
• Clean, readable, synthesizable Verilog RTL with synthesis/STA scripts
• Liberty timing model
• SDF back-annotated timing verification
• Layout abstract in LEF format
• GDSII with flat netlist for LVS
• LVS/DRC log files
• Documentation: specification sheet and integration/user guide

Applications

• Enterprise
• Mobile
• Consumer
• Automotive
• Internet of Things

• see the entire USB 3.0/2.0 PHY TSMC 28HPC datasheet
• get in contact with USB 3.0/2.0 PHY TSMC 28HPC Supplier